The present invention relates to housing semiconductor chips.
In recent years, considerable interest has been shown in pressure contacted insulated gate bipolar transistor (IGBT) power devices. Since the size and therefore the power rating of an individual chip is quite low, this requires that the encapsulation consists of an array of such chips, in contrast to more traditional pressure contacted power devices which always use a single large chip.
A number of ways of achieving this are known. In one such example, the chips are held in a fixed array by a frame of plastics material. In another, a frame is stuck on to a chip and the chips butted together on a molybdenum disk.
While both of these solutions have been shown to work, consideration of the movement and forces within the encapsulation due to thermal expansion show the potential to generate stress and wear, which potential increases with the size (i.e. power) of the encapsulation.
In the first example above, this comes about because the chips try to move their positions relative to the centre of the encapsulation with the expansion coefficient of the frame material, while the contacting copper pole pieces expand with the expansion coefficient of copper.
In the second example, the chips are butted together and the outer chips move with the coefficient of expansion of silicon and the molybdenum disk with its expansion coefficient, while the copper and molybdenum also show relative movement.
In all these cases, the relative movement is proportional to the distance from the centre of the encapsulation. As the encapsulated device is made larger, the movement on the outer chips increases.
As particular pieces of prior art, there may be mentioned EP-A-0 962 973, EP-A-0 746 023, EP-A-0 645 816, EP-A-0 637 080 and U.S. Pat. No. 5, 874, 774.
According to a first aspect of the present invention, there is provided a housing arrangement for a plurality of semiconductor chips, in which each of said chips is received in a respective frame to form a discrete sub-assembly, there being a first electrically conductive member, having portions which are in electrical connection with one face of each of the chips, and a second electrically conductive member, having portions which are in electrical connection with an opposite face of each of the chips, a local axis of each of said chips and its respective connecting portions being free to move by thermal expansion relative to such a local axis of any other of said chips and its connecting portions, substantially without transferring stress between any of said chips.
In each of the frames there may be respective contact shims between said faces of the respective chip and the respective connecting portions.
The frames may be shaped so that, for each two adjacent frames, a projection on one side wall face of one of them enters into a recess of a side wall face of the other.
At least some of the frames may each be formed with a channel receiving a contact pin for an electrode (e.g. a control electrode) of the respective chip.
According to a second aspect of the present invention, there is provided a housing arrangement for a plurality of semiconductor chips, in which each of said chips is received in a respective frame to form a discrete sub-assembly, there being a first electrically conductive member, having portions which are in electrical connection with one face of each of the chips, and a second electrically conductive member, having portions which are in electrical connection with an opposite face of each of the chips, wherein each frame engages a clip which acts to retain components within the frame.
The clip may engage with protrusions formed on side wall faces of the frame.
The frames and clips may be shaped so that, for each two adjacent frames, a protrusion and engaging clip portion on one side wall face of one frame enters into a recess of a side wall face of the other frame.